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背景：现有dwin屏在细节上显示有些许不足：1.在自动换行时无法单个单词截断 2.无法自动判断是否有超宽显示 3.无法多页显示 4.无法脱离触摸功能....等等；现基于不够完善之处开源一套使用者能自主控制并设计的迪文屏显示框架供大家参考，后续有时间会基于这套框架开源更多的ui显示界面
该框架优点：能够实现字符宽度计算、单词截断、自主控制换行、多页显示、多项菜单列表显示、动态菜单加载，文本超宽通过帮助信息显示未显示完全的字符、静态动态提示框多页显示且带指示条，并且可以无需触摸功能等等 ...
实现效果的视频链接: https://b23.tv/idvHyWM
以下是部分实现流程，具体请点击下载项目工程进行参考
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
const char msgInfoStr[] = {
"The ARM? Cortex?-M4 processor is a high performance embedded processor with DSP \
instructions which allow efficient signal processing and complex algorithm execution. It brings \
an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital \
signal control markets demand. The processor is highly configurable enabling a wide range \
of implementations from those requiring floating point operations, memory protection and \
powerful trace technology to cost sensitive devices requiring minimal area, while delivering \
outstanding computational performance and an advanced system response to interrupts.\n\
The advanced timer(TIMER0 & TIMER7) can be used as a three - phase PWM multiplexed \
on 6 channels.It has complementary PWM outputs with programmable dead - time generation. \
It can also be used as a complete general timer.The 4 independent channels can be used \
for input capture, output compare, PWM generation(edge - aligned or center - aligned counting \
modes) and single pulse mode output.If configured as a general 16 - bit timer, it has the same \
functions as the TIMERx timer.It can be synchronized with external signals or to interconnect \
with other general timers together which have the same architecture and features.\nIn deep-sleep mode, \
all clocks in the 1.2V domain are off, and all of the high speed \
crystal oscillator (IRC16M, HXTAL) and PLL are disabled. Only the contents of SRAM \
and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up \
the system from the deep-sleep mode including the 16 external lines, the RTC alarm, \
RTC Tamper and TimeStamp event, the LVD output, ENET wakeup, RTC wakeup and \
USB wakeup. When exiting the deep-sleep mode, the IRC16M is selected as the system \
clock.\nThe Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor \
core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are \
always active, and ensures proper operation starting from 2.4 V and down to 1.8V. The device \
remains in reset mode when VDD is below a specified threshold. The embedded low voltage \
detector (LVD) monitors the power supply, compares it to the voltage threshold and generates \
an interrupt as a warning message for leading the MCU into security."
};
const char* msgBoxButStr[3] = {
"OK",
"BACK",
"READ",
};
const char* msgBoxNoButStr[3] = {
NULL,
NULL,
NULL,
};
static char msgTitleStr[256];
void msgBoxShowBtnDemo(void)
{
strcpy(msgTitleStr, "DIWN SHOW MSGBOX");
dsi_msgboxShowStc_t disMsgBox;
memset(&disMsgBox, 0, sizeof(dsi_msgboxShowStc_t));
disMsgBox.infoAlignType = ALIGN_CENTER;
disMsgBox.titleStr = msgTitleStr;
disMsgBox.infoStr = (char*)msgInfoStr;
disMsgBox.langType = LANGUAGE_EN;
disMsgBox.startPage = 0;
disMsgBox.buttonNum = 3;
disMsgBox.buttonStr = (char**)msgBoxButStr;
disMsgBox.isFirst = true;
disMsgBox.isTimeOut=false;
disMsgBox.timeOverValue=0;
ui_ShowMsgBox(&disMsgBox);
}
void msgBoxShowNoBtnDemo1(void)
{
char infoBuff[4096];
int value = 0;
strcpy(msgTitleStr, "DIWN SHOW MSGBOX");
dsi_msgboxShowStc_t disMsgBox;
memset(&disMsgBox, 0, sizeof(dsi_msgboxShowStc_t));
disMsgBox.infoAlignType = ALIGN_LEFT;
disMsgBox.titleStr = msgTitleStr;
disMsgBox.langType = LANGUAGE_EN;
disMsgBox.startPage = 0;
disMsgBox.buttonNum = 0;
disMsgBox.buttonStr = (char**)msgBoxNoButStr;
disMsgBox.isFirst = true;
disMsgBox.isTimeOut=true;
disMsgBox.timeOverValue=1;
while (1)
{
memset(infoBuff, 0x0, sizeof(infoBuff));
sprintf(infoBuff, "%s %d", "Value = ", value);
disMsgBox.infoStr = infoBuff;
ui_ShowMsgBox(&disMsgBox);
value++;
if (disMsgBox.uRetBtnValue == CM_KEY_EXIT || disMsgBox.uRetBtnValue == CM_KEY_ENTER)
{
break;
}
}
}
void msgBoxShowNoBtnDemo2(void)
{
char infoBuff[4096];
int value = 0;
strcpy(msgTitleStr, "DIWN SHOW MSGBOX");
dsi_msgboxShowStc_t disMsgBox;
memset(&disMsgBox, 0, sizeof(dsi_msgboxShowStc_t));
disMsgBox.infoAlignType = ALIGN_CENTER;
disMsgBox.titleStr = msgTitleStr;
disMsgBox.langType = LANGUAGE_EN;
disMsgBox.startPage = 0;
disMsgBox.buttonNum = 0;
disMsgBox.buttonStr = (char**)msgBoxNoButStr;
disMsgBox.isFirst = true;
disMsgBox.isTimeOut=true;
disMsgBox.timeOverValue=1;
while (1)
{
memset(infoBuff, 0x0, sizeof(infoBuff));
sprintf(infoBuff, "%s %d", "Value = ", value);
disMsgBox.infoStr = infoBuff;
ui_ShowMsgBox(&disMsgBox);
value++;
if (disMsgBox.uRetBtnValue == CM_KEY_EXIT || disMsgBox.uRetBtnValue == CM_KEY_ENTER)
{
break;
}
}
}
void msgBoxShowNoBtnDemo3(void)
{
char infoBuff[4096];
int value = 0;
strcpy(msgTitleStr, "DIWN SHOW MSGBOX");
dsi_msgboxShowStc_t disMsgBox;
memset(&disMsgBox, 0, sizeof(dsi_msgboxShowStc_t));
disMsgBox.infoAlignType = ALIGN_RIGHT;
disMsgBox.titleStr = msgTitleStr;
disMsgBox.langType = LANGUAGE_EN;
disMsgBox.startPage = 0;
disMsgBox.buttonNum = 0;
disMsgBox.buttonStr = (char**)msgBoxNoButStr;
disMsgBox.isFirst = true;
disMsgBox.isTimeOut=true;
disMsgBox.timeOverValue=1;
while (1)
{
memset(infoBuff, 0x0, sizeof(infoBuff));
sprintf(infoBuff, "%s %d", "Value = ", value);
disMsgBox.infoStr = infoBuff;
ui_ShowMsgBox(&disMsgBox);
value++;
if (disMsgBox.uRetBtnValue == CM_KEY_EXIT || disMsgBox.uRetBtnValue == CM_KEY_ENTER)
{
break;
}
}
}
void msgBoxShowNoBtnDemo4(void)
{
char infoBuff[4096];
int value = 0;
strcpy(msgTitleStr, "DIWN SHOW MSGBOX");
dsi_msgboxShowStc_t disMsgBox;
memset(&disMsgBox, 0, sizeof(dsi_msgboxShowStc_t));
disMsgBox.infoAlignType = ALIGN_LEFT;
disMsgBox.titleStr = msgTitleStr;
disMsgBox.langType = LANGUAGE_EN;
disMsgBox.startPage = 0;
disMsgBox.buttonNum = 0;
disMsgBox.buttonStr = (char**)msgBoxNoButStr;
disMsgBox.isFirst = true;
disMsgBox.isTimeOut=true;
disMsgBox.timeOverValue=1;
while (1)
{
memset(infoBuff, 0x0, sizeof(infoBuff));
sprintf(infoBuff, "%s %d", "The ARM? Cortex?-M4 processor is a high performance embedded processor with DSP \
instructions which allow efficient signal processing and complex algorithm execution. It brings \
an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital \
signal control markets demand. The processor is highly configurable enabling a wide range \
of implementations from those requiring floating point operations, memory protection and \
powerful trace technology to cost sensitive devices requiring minimal area, while delivering \
outstanding computational performance and an advanced system response to interrupts.\n\
The advanced timer(TIMER0 & TIMER7) can be used as a three - phase PWM multiplexed \
on 6 channels.It has complementary PWM outputs with programmable dead - time generation. Value = ", value);
disMsgBox.infoStr = infoBuff;
ui_ShowMsgBox(&disMsgBox);
value++;
if (disMsgBox.uRetBtnValue == CM_KEY_EXIT || disMsgBox.uRetBtnValue == CM_KEY_ENTER)
{
break;
}
}
}
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define MENU_ITEM_TOTAL 76
const char* menuList[MENU_ITEM_TOTAL] = {
"The ARM? Cortex?-M4 processor is a high performance embedded processor with DSP \
instructions which allow efficient signal processing and complex algorithm execution. It brings \
an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital \
signal control markets demand. The processor is highly configurable enabling a wide range \
of implementations from those requiring floating point operations, memory protection and \
powerful trace technology to cost sensitive devices requiring minimal area, while delivering \
outstanding computational performance and an advanced system response to interrupts.",
"The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These \
include internal RC oscillator and external crystal oscillator, high speed and low speed two \
types. Several prescalers allow the frequency configuration of the AHB and two APB domains. \
The maximum frequency of the two AHB domains are 200 MHz. The maximum frequency of \
the two APB domains including APB1 is 50 MHz and APB2 is 100 MHz. See Figure 2-5. \
GD32F450xx clock tree for details on the clock tree.",
"The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor \
core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are \
always active, and ensures proper operation starting from 2.4 V and down to 1.8V. The device \
remains in reset mode when VDD is below a specified threshold. The embedded low voltage \
detector (LVD) monitors the power supply, compares it to the voltage threshold and generates \
an interrupt as a warning message for leading the MCU into security.",
"The boot loader is located in the internal 30KB of information blocks for the boot ROM memory \
(system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and \
PA10), USART2 (PB10 and PB11, or PC10 and PC11), and USBFS (PA9, PA10, PA11 and \
PA12) in device mode. It also can be used to transfer and update the Flash memory code, \
the data and the vector table sections. In default condition, boot from bank 0 of Flash memory \
is selected. It also supports to boot from bank 1 of Flash memory by setting a bit in option \
bytes.",
"The MCU supports three kinds of power saving modes to achieve even lower power \
consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating \
modes reduce the power consumption and allow the application to achieve the best balance \
between the CPU operating time, speed and power consumption",
"In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed \
crystal oscillator (IRC16M, HXTAL) and PLL are disabled. Only the contents of SRAM \
and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up \
the system from the deep-sleep mode including the 16 external lines, the RTC alarm, \
RTC Tamper and TimeStamp event, the LVD output, ENET wakeup, RTC wakeup and \
USB wakeup. When exiting the deep-sleep mode, the IRC16M is selected as the system \
clock.",
"Analog to digital converter (ADC)",
"Digital to analog converter (DAC)",
"General-purpose inputs/outputs (GPIOs)",
"Timers and PWM generation",
"The advanced timer (TIMER0 & TIMER7) can be used as a three-phase PWM multiplexed \
on 6 channels. It has complementary PWM outputs with programmable dead-time generation. \
It can also be used as a complete general timer. The 4 independent channels can be used \
for input capture, output compare, PWM generation (edge-aligned or center-aligned counting \
modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same \
functions as the TIMERx timer. It can be synchronized with external signals or to interconnect \
with other general timers together which have the same architecture and features.",
"Real time clock (RTC) and backup registers",
"216546575687",
"Inter-integrated circuit (I2C)",
"Serial peripheral interface (SPI)",
"The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio \
applications by 4-wire serial lines. GD32F450xx contain an I2S-bus interface that can be \
operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and \
SPI2. The audio sampling frequencies from 8 KHz to 192 KHz is supported.",
"Universal serial bus full-speed interface (USBFS)",
"Universal serial bus high-speed interface (USBHS)",
"Controller area network (CAN)",
"The ARM? Cortex?-M4 processor is a high performance embedded processor with DSP \
instructions which allow efficient signal processing and complex algorithm execution. It brings \
an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital \
signal control markets demand. The processor is highly configurable enabling a wide range \
of implementations from those requiring floating point operations, memory protection and \
powerful trace technology to cost sensitive devices requiring minimal area, while delivering \
outstanding computational performance and an advanced system response to interrupts.",
"The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These \
include internal RC oscillator and external crystal oscillator, high speed and low speed two \
types. Several prescalers allow the frequency configuration of the AHB and two APB domains. \
The maximum frequency of the two AHB domains are 200 MHz. The maximum frequency of \
the two APB domains including APB1 is 50 MHz and APB2 is 100 MHz. See Figure 2-5. \
GD32F450xx clock tree for details on the clock tree.",
"The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor \
core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are \
always active, and ensures proper operation starting from 2.4 V and down to 1.8V. The device \
remains in reset mode when VDD is below a specified threshold. The embedded low voltage \
detector (LVD) monitors the power supply, compares it to the voltage threshold and generates \
an interrupt as a warning message for leading the MCU into security.",
"The boot loader is located in the internal 30KB of information blocks for the boot ROM memory \
(system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and \
PA10), USART2 (PB10 and PB11, or PC10 and PC11), and USBFS (PA9, PA10, PA11 and \
PA12) in device mode. It also can be used to transfer and update the Flash memory code, \
the data and the vector table sections. In default condition, boot from bank 0 of Flash memory \
is selected. It also supports to boot from bank 1 of Flash memory by setting a bit in option \
bytes.",
"The MCU supports three kinds of power saving modes to achieve even lower power \
consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating \
modes reduce the power consumption and allow the application to achieve the best balance \
between the CPU operating time, speed and power consumption",
"In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed \
crystal oscillator (IRC16M, HXTAL) and PLL are disabled. Only the contents of SRAM \
and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up \
the system from the deep-sleep mode including the 16 external lines, the RTC alarm, \
RTC Tamper and TimeStamp event, the LVD output, ENET wakeup, RTC wakeup and \
USB wakeup. When exiting the deep-sleep mode, the IRC16M is selected as the system \
clock.",
"Analog to digital converter (ADC)",
"Digital to analog converter (DAC)",
"General-purpose inputs/outputs (GPIOs)",
"Timers and PWM generation",
"The advanced timer (TIMER0 & TIMER7) can be used as a three-phase PWM multiplexed \
on 6 channels. It has complementary PWM outputs with programmable dead-time generation. \
It can also be used as a complete general timer. The 4 independent channels can be used \
for input capture, output compare, PWM generation (edge-aligned or center-aligned counting \
modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same \
functions as the TIMERx timer. It can be synchronized with external signals or to interconnect \
with other general timers together which have the same architecture and features.",
"Real time clock (RTC) and backup registers",
"216546575687",
"Inter-integrated circuit (I2C)",
"Serial peripheral interface (SPI)",
"The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio \
applications by 4-wire serial lines. GD32F450xx contain an I2S-bus interface that can be \
operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and \
SPI2. The audio sampling frequencies from 8 KHz to 192 KHz is supported.",
"Universal serial bus full-speed interface (USBFS)",
"Universal serial bus high-speed interface (USBHS)",
"Controller area network (CAN)",
"The ARM? Cortex?-M4 processor is a high performance embedded processor with DSP \
instructions which allow efficient signal processing and complex algorithm execution. It brings \
an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital \
signal control markets demand. The processor is highly configurable enabling a wide range \
of implementations from those requiring floating point operations, memory protection and \
powerful trace technology to cost sensitive devices requiring minimal area, while delivering \
outstanding computational performance and an advanced system response to interrupts.",
"The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These \
include internal RC oscillator and external crystal oscillator, high speed and low speed two \
types. Several prescalers allow the frequency configuration of the AHB and two APB domains. \
The maximum frequency of the two AHB domains are 200 MHz. The maximum frequency of \
the two APB domains including APB1 is 50 MHz and APB2 is 100 MHz. See Figure 2-5. \
GD32F450xx clock tree for details on the clock tree.",
"The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor \
core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are \
always active, and ensures proper operation starting from 2.4 V and down to 1.8V. The device \
remains in reset mode when VDD is below a specified threshold. The embedded low voltage \
detector (LVD) monitors the power supply, compares it to the voltage threshold and generates \
an interrupt as a warning message for leading the MCU into security.",
"The boot loader is located in the internal 30KB of information blocks for the boot ROM memory \
(system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and \
PA10), USART2 (PB10 and PB11, or PC10 and PC11), and USBFS (PA9, PA10, PA11 and \
PA12) in device mode. It also can be used to transfer and update the Flash memory code, \
the data and the vector table sections. In default condition, boot from bank 0 of Flash memory \
is selected. It also supports to boot from bank 1 of Flash memory by setting a bit in option \
bytes.",
"The MCU supports three kinds of power saving modes to achieve even lower power \
consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating \
modes reduce the power consumption and allow the application to achieve the best balance \
between the CPU operating time, speed and power consumption",
"In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed \
crystal oscillator (IRC16M, HXTAL) and PLL are disabled. Only the contents of SRAM \
and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up \
the system from the deep-sleep mode including the 16 external lines, the RTC alarm, \
RTC Tamper and TimeStamp event, the LVD output, ENET wakeup, RTC wakeup and \
USB wakeup. When exiting the deep-sleep mode, the IRC16M is selected as the system \
clock.",
"Analog to digital converter (ADC)",
"Digital to analog converter (DAC)",
"General-purpose inputs/outputs (GPIOs)",
"Timers and PWM generation",
"The advanced timer (TIMER0 & TIMER7) can be used as a three-phase PWM multiplexed \
on 6 channels. It has complementary PWM outputs with programmable dead-time generation. \
It can also be used as a complete general timer. The 4 independent channels can be used \
for input capture, output compare, PWM generation (edge-aligned or center-aligned counting \
modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same \
functions as the TIMERx timer. It can be synchronized with external signals or to interconnect \
with other general timers together which have the same architecture and features.",
"Real time clock (RTC) and backup registers",
"216546575687",
"Inter-integrated circuit (I2C)",
"Serial peripheral interface (SPI)",
"The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio \
applications by 4-wire serial lines. GD32F450xx contain an I2S-bus interface that can be \
operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and \
SPI2. The audio sampling frequencies from 8 KHz to 192 KHz is supported.",
"Universal serial bus full-speed interface (USBFS)",
"Universal serial bus high-speed interface (USBHS)",
"Controller area network (CAN)",
"The ARM? Cortex?-M4 processor is a high performance embedded processor with DSP \
instructions which allow efficient signal processing and complex algorithm execution. It brings \
an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital \
signal control markets demand. The processor is highly configurable enabling a wide range \
of implementations from those requiring floating point operations, memory protection and \
powerful trace technology to cost sensitive devices requiring minimal area, while delivering \
outstanding computational performance and an advanced system response to interrupts.",
"The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These \
include internal RC oscillator and external crystal oscillator, high speed and low speed two \
types. Several prescalers allow the frequency configuration of the AHB and two APB domains. \
The maximum frequency of the two AHB domains are 200 MHz. The maximum frequency of \
the two APB domains including APB1 is 50 MHz and APB2 is 100 MHz. See Figure 2-5. \
GD32F450xx clock tree for details on the clock tree.",
"The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor \
core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are \
always active, and ensures proper operation starting from 2.4 V and down to 1.8V. The device \
remains in reset mode when VDD is below a specified threshold. The embedded low voltage \
detector (LVD) monitors the power supply, compares it to the voltage threshold and generates \
an interrupt as a warning message for leading the MCU into security.",
"The boot loader is located in the internal 30KB of information blocks for the boot ROM memory \
(system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and \
PA10), USART2 (PB10 and PB11, or PC10 and PC11), and USBFS (PA9, PA10, PA11 and \
PA12) in device mode. It also can be used to transfer and update the Flash memory code, \
the data and the vector table sections. In default condition, boot from bank 0 of Flash memory \
is selected. It also supports to boot from bank 1 of Flash memory by setting a bit in option \
bytes.",
"The MCU supports three kinds of power saving modes to achieve even lower power \
consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating \
modes reduce the power consumption and allow the application to achieve the best balance \
between the CPU operating time, speed and power consumption",
"In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed \
crystal oscillator (IRC16M, HXTAL) and PLL are disabled. Only the contents of SRAM \
and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up \
the system from the deep-sleep mode including the 16 external lines, the RTC alarm, \
RTC Tamper and TimeStamp event, the LVD output, ENET wakeup, RTC wakeup and \
USB wakeup. When exiting the deep-sleep mode, the IRC16M is selected as the system \
clock.",
"Analog to digital converter (ADC)",
"Digital to analog converter (DAC)",
"General-purpose inputs/outputs (GPIOs)",
"Timers and PWM generation",
"The advanced timer (TIMER0 & TIMER7) can be used as a three-phase PWM multiplexed \
on 6 channels. It has complementary PWM outputs with programmable dead-time generation. \
It can also be used as a complete general timer. The 4 independent channels can be used \
for input capture, output compare, PWM generation (edge-aligned or center-aligned counting \
modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same \
functions as the TIMERx timer. It can be synchronized with external signals or to interconnect \
with other general timers together which have the same architecture and features.",
"Real time clock (RTC) and backup registers",
"216546575687",
"Inter-integrated circuit (I2C)",
"Serial peripheral interface (SPI)",
"The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio \
applications by 4-wire serial lines. GD32F450xx contain an I2S-bus interface that can be \
operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and \
SPI2. The audio sampling frequencies from 8 KHz to 192 KHz is supported.",
"Universal serial bus full-speed interface (USBFS)",
"Universal serial bus high-speed interface (USBHS)",
"Controller area network (CAN)",
};
static char menuTitleStr[256];
void menu_ShowDemo1(void)
{
strcpy(menuTitleStr, "DIWN SHOW MENU");
dsi_menuShowStc_t disMenu;
memset(&disMenu, 0, sizeof(dsi_menuShowStc_t));
disMenu.itemAlignType = ALIGN_LEFT;
disMenu.titleStr = menuTitleStr;
disMenu.pItemListStr = (char **)menuList;
disMenu.totalItem = MENU_ITEM_TOTAL;
disMenu.langType = LANGUAGE_EN;
disMenu.startCursor = 5;
disMenu.isTimeOut = false;
disMenu.timeOverValue = 0;
ui_ShowMenu(&disMenu);
}
void menu_ShowDemo2(void)
{
strcpy(menuTitleStr, "DIWN SHOW MENU");
dsi_menuShowStc_t disMenu;
memset(&disMenu, 0, sizeof(dsi_menuShowStc_t));
disMenu.itemAlignType = ALIGN_LEFT;
disMenu.titleStr = menuTitleStr;
disMenu.pItemListStr = (char**)menuList;
disMenu.totalItem = 0;
disMenu.langType = LANGUAGE_EN;
disMenu.startCursor = 0;
disMenu.isTimeOut = true;
disMenu.timeOverValue = 500;
while (1)
{
if (disMenu.totalItem > MENU_ITEM_TOTAL-1)
{
disMenu.isTimeOut = false;
disMenu.timeOverValue = 0;
}
else
{
disMenu.totalItem++;
disMenu.startCursor = disMenu.totalItem - 1;
}
ui_ShowMenu(&disMenu);
if (disMenu.uRetBtnValue == CM_KEY_EXIT || disMenu.uRetBtnValue == CM_KEY_ENTER)
{
break;
}
}
部分效果图：
}
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|Archiver|手机版|小黑屋|迪文科技论坛
( 京ICP备05033781号-1 )
发表于 2022-8-27 23:02:43
楼主
,是迪文屏太好玩了
